Один машинный цикл оригинального ядра занимает 12 временных тактов, а большинство инструкций выполняется за один или два машинных цикла. При частоте тактового генератора, равной 12 МГц , ядро может выполнять 1 миллион операций в секунду , выполняемых за один цикл, или тысяч операций в секунду, выполняемых за два цикла. Улучшенное совместимое ядро, которое в настоящее время распространено, выполняет машинный цикл за шесть, четыре, два, или даже за один временной такт, и позволяет использовать тактовые генераторы с частотой до МГц, что позволило увеличить количество выполняемых операций в секунду. Все совместимые устройства, производимые SILabs , некоторые из производимых Dallas и немногие из производимых Atmel имеют ядро с 1 тактом на машинный цикл. Чрезвычайно полезной особенностью ядра является обработка булевых данных, что позволило ввести бинарную логику, оперирующую напрямую с битами внутренней ОЗУ области из прямо-адресуемых битов и регистров. Данная особенность была востребована в приложениях промышленной автоматики.
|Published (Last):||7 June 2016|
|PDF File Size:||15.63 Mb|
|ePub File Size:||13.48 Mb|
|Price:||Free* [*Free Regsitration Required]|
About [ edit ] The Intel is an 8-bit microcontroller which means that most available operations are limited to 8 bits. There are 3 basic "sizes" of the Short, Standard, and Extended. The Short and Standard chips are often available in DIP dual in-line package form, but the Extended models often have a different form factor, and are not "drop-in compatible".
All these things are called because they can all be programmed using assembly language, and they all share certain features although the different models all have their own special features. Some of the features that have made the popular are: 4 KB on chip program memory. Bit as well as byte addressable RAM area of 16 bytes. Four 8-bit ports, short models have two 8-bit ports. Typical applications[ edit ] chips are used in a wide variety of control systems, telecom applications, robotics as well as in the automotive industry.
Pin should be held high for 2 machine cycles. PIN 30 is called ALE address latch enable , which is used when multiple memory chips are connected to the controller and only one of them needs to be selected. We will deal with this in depth in the later chapters. This is "program store enable". Pin If we use an external ROM then it should have a logic 0 which indicates Micro controller to read data from memory.
If we use multiple memory chips then this pin is used to distinguish between them. Pin If we have to use multiple memories then by applying logic 1 to this pin instructs Micro controller to read data from both memories first internal and afterwards external. The other ports P0, P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage.
When 1s are written to portn1 pins are pulled high by the internal pull-ups and can be used as inputs. P0 acts as AD0-AD7, as can be seen from fig 1. Oscillator Circuits[ edit ] The requires an external oscillator circuit. The oscillator circuit generates the clock pulses so that all internal operations are synchronized. One machine cycle has 6 states. One state is 2 T-states. Therefore one machine cycle is 12 T-states. Time to execute an instruction is found by multiplying C by 12 and dividing product by Crystal frequency.
When stored on EEPROM or Flash, the program memory can be rewritten when the microcontroller is in the special programmer circuit or, if not using a , through a preinstalled bootloader. Program Start Address[ edit ] The starts executing program instructions from address in the program memory. This area of memory cannot be used for data or program storage, but is instead a series of memory-mapped ports and registers.
All port input and output can therefore be performed by memory mov operations on specified addresses in the SFR. Also, different status registers are mapped into the SFR, for use in checking the status of the , and changing some operational parameters of the General Purpose Registers[ edit ] The has 4 selectable banks of 8 addressable 8-bit registers, R0 to R7.
This means that there are essentially 32 available general purpose registers, although only 8 one bank can be directly accessed at a time. To access the other banks, we need to change the current bank number in the flag register. The A register works in a similar fashion to the AX register of x86 processors.
The A register is called the accumulator, and by default it receives the result of all arithmetic operations. The B register is used in a similar manner, except that it can receive the extended answers from the multiply and divide operations. When not being used for multiplication and Division, the B register is available as an extra general-purpose register.
The A and B registers can store up to 8-bits of data each.
Power saving mode on some derivatives One feature of the core is the inclusion of a boolean processing engine which allows bit -level boolean logic operations to be carried out directly and efficiently on select internal registers , ports and select RAM locations. Another feature is the inclusion of four bank selectable working register sets which greatly reduce the amount of time required to perform the context switches to enter and leave interrupt service routines. With one instruction, the can switch register banks, avoiding the time consuming task of transferring the critical registers to RAM. The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks. Derivative features[ edit ] As of [update] , new derivatives are still developed by many major chipmakers, and major compiler suppliers such as IAR Systems , Keil and Altium Tasking continuously release updates.
Embedded Systems/8051 Microcontroller